1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a method for fabricating an integrated circuit having an improved memory cell that includes a base gate, an intergate dielectric, and a spacer gate, and to an integrated circuit capable of being manufactured by such a method.
2. Description of the Related Art
Memory circuits can be used to store and retrieve large quantities of electronic information. The term non-volatile memory is used to classify those memory circuits that are capable of retaining information when the power supply is interrupted for a substantial amount of time. Non-volatile memory can be formed using bipolar or metal oxide semiconductor ("MOS") technologies. These memory circuits are generally structured as read-only memory ("ROM"). ROMs are memories in which the data retrieval time is relatively short, but the data entry time is relatively long (if data entry is possible at all). Masked ROMs, generally referred to only as ROMs, are memories into which data is entered during manufacturing and cannot be subsequently altered. Conversely, programmable ROMs ("PROMs") allow entry of data after manufacturing is complete. Examples of MOS PROM types include erasable programmable ROM ("EPROM"), electrically erasable programmable ROM ("EEPROM"), and flash memory EEPROM ("FLASH EEPROM").
Non-volatile MOS PROMs can be fabricated using many well-known technologies such as floating gate tunnel oxide ("FLOTOX"), textured polysilicon, metal nitride oxide silicon ("MNOS"), and EPROM--tunnel oxide ("ETOX"). How each memory cell type is programmed and erased depends on the technology used. For example, a FLOTOX EEPROM memory cell is generally programmed (moving electrons into the floating gate) by biasing the control gate, and such a memory cell is generally erased (moving electrons out of the floating gate) by biasing the drain. Conversely, in MNOS memory cells charge is stored in discrete traps in the bulk of a nitride layer formed above a thin oxide layer. Programming and erasure are accomplished by inducing electron tunneling between the nitride bulk and the substrate.
FIG. 1 illustrates a FLOTOX EEPROM memory cell according to a conventional design. The FLOTOX cell includes a relatively thin tunneling oxide 102 interposed between a doped polysilicon floating gate 104 and a silicon substrate 100. Tunneling oxide 102 is typically thermally grown upon substrate 100 to a thickness of less than, for example, 100 angstroms. The FLOTOX cell further includes an interpoly oxide 106 arranged upon floating gate 104 and underlying a doped polysilicon control gate 108. Fabrication of the FLOTOX cell may involve forming these layers above silicon substrate 100 and then etching away portions of the layers not masked by a patterned photoresist layer to form the stacked structure shown in FIG. 1. A heavily concentrated dopant distribution that is self-aligned to the opposed sidewalls of the stacked structure may then be forwarded into substrate 100 to form source and drain regions 110 and 112, respectively. An oxide layer 114 may be thermally grown upon the periphery of the stacked structure and upon exposed regions of substrate 100. Due to exposure to thermal radiation during this process, the impurities within source and drain regions 110 and 112 undergo lateral migration toward the channel region underneath tunneling oxide 102, resulting in the configuration depicted in FIG. 1.
In subsequent processing, control gate 108 can be coupled to a word line conductor and bit line conductors can be formed within contact windows of oxide layer 114 for contacting drain region 112. Floating gate 104 can be programmed by grounding source and drain regions 110 and 112 and applying a relatively high voltage to control gate 108. During programming, electrons from the substrate pass through tunneling oxide 102 to floating gate 104 by a tunneling mechanism known as Fowler-Nordheim tunneling. As more electrons accumulate in floating gate 104, the electric field is reduced and the flow of electrons to floating gate 104 decreases. Programming of the memory cell is performed for a time sufficient to build up a desired charge level on the floating gate. Discharge of floating gate 104 to erase the cell can be achieved by grounding control gate 108, floating gate 104, and source region 110 and applying a relatively high voltage to drain region 112.
Because of the desire to build faster and more complex integrated circuits, it is beneficial to increase the capacitances of the memory cell dielectric layers between gates (e.g., interpoly dielectric 106) and between a gate and the substrate (e.g., tunneling oxide 102). Higher capacitances can allow, for example, the use of lower voltages to induce electron tunneling from the substrate to the floating gate. The capacitance per unit area, C, of a dielectric layer can be expressed as: EQU C=.epsilon./t
where .epsilon. is the permittivity of the dielectric layer and t is the thickness of the dielectric layer. The above equation for C demonstrates that the capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric and inversely proportional to the thickness of the dielectric.
The permittivity, .epsilon., of a material can be normalized to the permittivity of vacuum, .epsilon..sub.0, to determine the relative permittivity of the material. Relative permittivity, or dielectric constant, k, is typically used in place of permittivity. The dielectric constant of a material is defined as: EQU k=.epsilon./.epsilon..sub.0
As such, the dielectric layer thickness necessary to bring about a certain level of capacitive coupling is highly dependent on the k value of the dielectric layer. Dielectric layers with relatively low k values generally must be thinner than dielectric layers with relatively high k values to achieve similar results.
Silicon dioxide ("oxide") has a relatively low k value of less than about 4.0 (usually about 3.7 to 3.8). Consequently, a tunneling dielectric or interpoly dielectric composed of silicon dioxide may need to be made very thin (e.g., less than 100 angstroms in the case of tunneling oxides) to achieve the capacitance desired. Manufacturing reliable silicon dioxide layers at such low thicknesses, however, is difficult. As a result, thin layers of silicon dioxide often contain pinholes and/or localized voids that can adversely effect device properties.
In addition, both programming and erasure of FLOTOX EEPROM and other conventional memory cells generally involve the transfer of electrons to and from a semiconducting substrate (as described above). Such memory cells must be formed, therefore, in the substrate plane. (For the purpose of this disclosure, "substrate plane"may be considered to refer to the level of devices that are formed within, upon, or just above a substrate.) Electron transfer in these conventional memory cells often occurs between junctions (e.g., source region 110 and drain region 112) and a conductive gate (e.g., floating gate 104). The space available in the substrate plane is limited, of course, by the surface area of the substrate, and the junctions occupy valuable real estate. Furthermore, numerous non-memory devices may also need to be formed in the substrate plane. The space available in this plane for the formation of conventional memory cells, consequently, is often undesirably limited.
Therefore, it would be desirable to design a memory cell that does not need to transfer electrons between a semiconducting substrate during operation. Such a memory cell would not be required to be in the substrate plane. It would also be advantageous to incorporate dielectric layers with higher capacitances per unit area than conventionally formed silicon dioxide layers. An integrated circuit containing such a memory cell could have a higher memory density and greater reliability than conventional memory circuits.